Recently, integrated circuit density has been growing exponentially every year in accordance with Moore's law, so that circuit designs have become more and more complex. Today, the mainstream of integrated-circuit design is register-transfer level (RTL) design using a hardware description language (HDL). RTL design provides a higher level of design abstraction compared with gate-level design, but it is becoming more difficult to handle the circuit size that is increasing year by year.
Thus, high-level synthesis (also referred to as “high-level design”) which provides a still higher level of abstraction than RTL is now increasingly being used. The input languages (for example, high-level languages) that are often used in high-level synthesis are software languages. In particular, C, C++, and SystemC as a class library for hardware description are most often used. There are also other input languages, such as Java (registered trademark), BASIC, assembly language, and the like. In high-level synthesis, other than a high-level language, an HDL such as VHDL (Very High Speed Integrated Circuit (VHSIC) HDL), Verilog HDL, SystemVerilog, and the like is created by referring to constraints and technology libraries.
In high-level synthesis, the provider provides a source code representing design data of a semiconductor device (or a semiconductor circuit) to the user, and the user performs high-level synthesis and simulation based on the source code.
In RTL design using an HDL, the original HDL is not easily reproduced from a netlist generated by logic synthesis. Further, since a mechanism for encrypting as compiler identifiers for HDL is supported, it is possible to directly use the encrypted HDL in RTL simulation and logic synthesis by electronic design automation (EDA) tools. Accordingly, the provider provides a netlist and encrypted HDL to the user, instead of providing non-encrypted HDL describing the design data.
Examples of the related art are disclosed in Japanese Laid-open Patent Publications No. 2003-99409, No. 2011-170602, and No. 2010-146577.
In high-level synthesis, design is made using a software language having a higher level of abstraction than RTL. Therefore, a source code representing the design data is easily readable by humans. In the case of conventional high-level synthesis, such a source code that is easily readable by humans is provided to the user, which might result in the outflow of know-how (intellectual properties) of the provider.